Wafer level interposer

ABSTRACT

Double-sided interposer assemblies and methods for forming and using them. In one example of the invention, an interposer comprises a substrate having a first surface and a second surface opposite of said first surface, a first plurality of contact elements disposed on said first side of said substrate, and a second plurality of contact elements disposed on said second surface of said substrate, wherein said interposer connects electronic devices via said first and said second plurality of contact elements.

FIELD OF THE INVENTION

The present invention generally relates to wafer level interposers, andmore particularly to interposers having double-sided contact elementsfor interfacing two electrical devices, and to methods for making suchinterposers.

BACKGROUND OF THE INVENTION

There are numerous interposers and methods for making and using theseinterposers in the prior art. Interposers are used for differentpurposes. Generally, interposers provide an interface between twoelectrical components, such as one or more semiconductor devices and aprinted circuit board, or two printed circuit boards. For example, aninterposer can be used to interface a semiconductor wafer to a probecard for testing of the dies on the wafer to determine which dies aregood. A wafer tester or prober may be advantageously employed to make aplurality of discrete pressure connections to a like plurality ofdiscrete contact elements (e.g. bonding pads) on the dies. In thismanner, the semiconductor dies can be tested, for example, to determinewhether the dies are non-functional or partially functional (each, “bad”die), prior to singulating the dies from the wafer.

Testing of semiconductor devices is performed on various levels. Forexample, in very advanced systems, semiconductor devices may be testedfor performance operations, while still in wafer form, under varioustemperature and environmental conditions. This type of testing iscommonly referred to as “wafer level test.” Referring to FIG. 1, a testassembly 100 is shown to illustrate a technique for performingwafer-level test and/or wafer level burn-in of semiconductor devicesincluded in a test substrate (application specific integrated circuits(ASIC) 106 and base plate 108, collectively) having active electroniccomponents such as ASICs 106 a-106 d, mounted to an interconnectionsubstrate or incorporated therein. See commonly assigned U.S. Pat. No.6,064,213 entitled “ Wafer-Level Burn-In and Test”, which is hereinincorporated by reference as though set forth in full. Spring contactelements 110 effect interconnections between the ASICs 106 a-106 d(ASICs 106 a-106 d generally comprise the ASICs 106) and a plurality ofdevices-under-test (DUTs), 102 a-102 d, on a wafer-under-test (WUT) 102.In one embodiment, the assembly is disposed in a vacuum vessel withindependent temperature regulation so that the ASICs can be operated attemperatures independent from and in many instances significantly lowerthan the burn-in temperature of the DUTs. The spring contact elements110 may be mounted to either the DUTs 102 a-102 d or the ASICs 106 a-106d, and may fan out to relax tolerance constraints on aligning andinterconnecting the ASICs 106 and the DUTs 102. For the connection 120to the host controller, a significant reduction in interconnect countand consequent simplification of the interconnection substrate isrealized because the ASICs are capable of receiving a plurality ofsignals for testing the DUTs over relatively few signal lines from ahost controller 116 and promulgating these signals over the relativelymany interconnections 110 between the ASICs 106 and the DUTs 102. TheASICs 106 can also generate at least a portion of these signals inresponse to control signals from the host controller 116. Physicalalignment techniques are also described in the reference.

During testing, a power supply 118 provides power signals to the ASICsthrough a base plate 108 connected to an upper portion of a chuck 104 aused for holding the test assembly in place with the assistance of guidepins 112. While operational, i.e. under test, force is applied in thez-direction bringing the ASICs 106 in contact with the spring contactelement 610 and compressing the latter to a position determined bycompression stops 114, which are positioned at either end of the wafer102. The compression stops function to stop the base plate 108 frommoving down in the z-direction thereby determining the extent to whichthe spring contact elements 110 are compressed and thus avoidingover-compression of the latter.

FIG. 2 illustrates an alternative test assembly 200 including a wafer202, an interposer 204 and a tester contactor 206. On both surfaces ofthe interposer, solder balls 210 are formed in order to interconnectwafer 202 to tester contactor 206. The contact pads 208 on wafer 202come in contact with solder balls 210 on the top surface of interposer204 when wafer 202 is lowered toward tester contactor 206. Upon furtherlowering of wafer 202, solder balls 212 on the bottom surface ofinterposer 204 come in contact with the contact pads 214 of the testercontactor 206, thereby establishing electrical connection between wafer202 and the tester through tester contactor 206. Typically, a wafer canhave in excess of 10,000 contact pads. For instance, a 200 mm wafer mayhave 20-50 thousand contact pads. To establish reliable connectionsbetween such a large number of contact pads between the wafer and thetester is a significant challenge.

In prior art wafer-level testing techniques, the interconnectionelements reside on the wafer or the contactor (wiring layer). While thisprior art approach provides certain advantages, it also has certainlimitations. For example, when the interconnection elements or springsreside on the wafer or contactor, a modular construction approach cannotbe implemented for a burn-in system. Similarly, the use of solder ballson the interposer does not permit a modular construction.

It is noted that there are certain existing double-sided interconnectionsubstrates, such as shown in commonly assigned U.S. Pat. No. 5,917,707,entitled “Flexible Contact Structure With An Electrically ConductiveShell” (for example, FIG. 36), and commonly assigned U.S. patentapplication Ser. No. 08/452,255, entitled Electrical Contact StructuresFormed By Configuring A Flexible Wire To Have A Springable Shape AndCovercoating The Wire With At Least One Layer Of A Resilient ConductiveMaterial, Methods Of Mounting The Contact Structures To ElectronicComponents, And Applications For Employing The Contact Structures” (forexample, FIG. 39). These prior art substrates, however, do not addresscompletely certain wafer-level testing needs.

A need therefore exists for an improved interposer and a method formaking and using the same without the need to connect resilientinterconnect elements or other types of interconnect elements onto theDUT and/or the device being packaged.

SUMMARY OF THE INVENTION

The present invention provides a method for testing a semiconductordevice wafer comprising connecting a first side of an interposer havinga first plurality of resilient contact elements disposed thereon to thewafer, connecting a second side of an interposer having a secondplurality of resilient contact elements disposed thereon to a wiringlayer and providing a pathway for signals from the wafer going to andfrom the wiring layer thereby permitting exercising of devices on thewafer.

A method of the present invention also enables performing wafer-levelburn-in and test of a plurality of semiconductor devices (DUTs) residenton a semiconductor wafer. This includes providing a plurality of activeelectronic components having terminals on a surface thereof andproviding an interposer for effecting direct electrical connectionsbetween terminals of the plurality of DUTs and the terminals of theactive electronic components.

In another embodiment of the present invention, a method is provided forforming an interposer by providing a substrate having a first surfaceand a second surface, the second surface being opposite of the firstsurface, forming a first plurality of contact elements on the firstsurface of the substrate and forming a second plurality of contactelements on the second surface of the substrate.

A test assembly in accordance with the present invention comprises awiring substrate having a first surface, a second surface and aplurality of contact terminals on the first surface thereof, aninterposer having a first surface, a second surface, a plurality ofcontact pads disposed on the first and the second surface thereof, and afirst plurality of resilient contact structures mounted adjacent to andextending from the first surface thereof and a second plurality ofresilient contact structures mounted adjacent to and extending from thesecond surface thereof. The interposer provides electrical connectionbetween the wiring surface and the wafer by engaging the contact pads ofthe wiring surface with the first plurality of resilient contactstructures and the contact pads of the wafer with the second pluralityof resilient contact structures.

Various other assemblies and methods are described below in conjunctionwith the following figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and notlimitation in the figures of the accompanying drawings in which likereferences indicate similar elements.

FIG. 1 shows a prior art test assembly for performing wafer-levelburn-in and testing of semiconductor devices included on a testsubstrate.

FIG. 2 illustrates a prior art test assembly including an interposerwith solder balls attached to both surfaces thereof.

FIG. 3 a shows an interconnect assembly including an interposer withcompression stops in accordance with an embodiment of the presentinvention.

FIG. 3 b shows an interconnect assembly including a freely floatinginterposer without any compression stops in accordance with anembodiment of the present invention.

FIG. 4 a shows an interposer with identical set of resilient contactelements on both surfaces thereof, but also including displacement ofcontacts so that the relationship between upward and downward contactsis not 1:1 in accordance with an embodiment of the present invention.

FIG. 4 b shows an interposer with different sets of resilient contactelements on both surfaces thereof, according to the present inventionbut including pitch spreading from one set of resilient contacts to theother.

FIG. 4 c shows an interposer including passive components on the lowersurface of the interposer substrate in accordance with an embodiment ofthe present invention.

FIG. 4 d shows an interposer including components on both sides of theinterposer substrate in accordance with an embodiment of the presentinvention.

FIG. 5 is a cross-sectional view of an embodiment of a generic spacetransformer in accordance with an embodiment of the present invention.

FIGS. 6 a-6 f are side cross-sectional views illustrating fabricatingcapture pads that are hourglass-like through-holes in a substrate inaccordance with an embodiment of the present invention.

FIG. 6 g is a schematic illustration of a step in the process describedwith respect to FIGS. 6 a-6 f in accordance with an embodiment of thepresent invention.

FIG. 6 h is a schematic illustration of an alternate step in the processdescribed with respect to FIGS. 6 a-6 f in accordance with an embodimentof the present invention.

FIG. 6 i is a side cross-sectional view of a socket substrate that hasbeen made using the procedure set forth in FIG. 6 h in accordance withan embodiment of the present invention.

FIG. 7 a is a side view of an electronic component being joined with tipstructures in accordance with an embodiment of the present invention.

FIG. 7 b is a side view of a further step in joining an electroniccomponent with tip structures in accordance with an embodiment of thepresent invention.

FIG. 8 a is a side, cross-sectional view of an embodiment wherein thecontact tip structures of the present invention are affixed to a type ofelongate interconnection elements in accordance with an embodiment ofthe present invention.

FIG. 8 b is a perspective view of a contact tip structure, which hasbeen joined to an interconnection element in accordance with anembodiment of the present invention.

FIG. 8 c is a perspective view of a contact tip structure joined to anend of an interconnection element in accordance with an embodiment ofthe present invention.

FIG. 9 a shows an interconnect assembly including an interposer having aplurality of passive and/or active elements in accordance with anembodiment of the present invention.

FIG. 9 b shows an interconnect assembly including an assembly having aplurality of passive and/or active elements mounted on the die and thewafer contactor in accordance with an embodiment of the presentinvention.

FIGS. 10 a and 10 b are side cross-sectional and perspective views,respectively, of a completed contact structure formed on an electroniccomponent in accordance with an embodiment of a process for making acontact structure.

FIG. 11 shows an interposer having disposed a set of solder balls on oneof its surfaces for interconnecting to another electronic component inaccordance with an embodiment of the present invention.

FIG. 12 shows an interposer having disposed on one of its surfaces aplurality of spring contact elements that are fabricated rather thancomposite in accordance with an embodiment of the present invention.

FIG. 13 shows an interposer interconnecting two sets of tile substratesin accordance with an embodiment of the present invention.

FIG. 14 shows an interposer wherein two different types of contactelements are employed on the top and bottom surfaces of the interposerin accordance with an embodiment of the present invention.

FIG. 15 shows an interconnect assembly including an interposer with theimplementation of a pressure actuated contactor in accordance with anembodiment of the present invention.

FIG. 16 shows an interposer interconnecting a plurality of DUTs to aplurality of ASICs in accordance with an embodiment of the presentinvention.

FIG. 17 shows an interconnect assembly including a host controller, apower supply and a vacuum vessel in accordance with an embodiment of thepresent invention.

FIG. 18 a shows an interposer comprising a substrate and variousbeam-type resilient contact elements in accordance with an embodiment ofthe present invention.

FIG. 18 b shows an interposer assembly including contact elements andcompression stops in various positions in accordance with an embodimentof the present invention.

DETAILED DESCRIPTION

The present invention relates to an interposer having resilientinterconnect elements disposed upon two surfaces of a substrate forcontacting a wafer having a plurality of dies disposed thereupon, and totechniques for fabricating such an interposer. As will be evident fromthe description that follows, techniques of fabricating an interposerinvolve fabricating interconnect elements directly upon the interposersubstrate, or transferring elements of them to the interposer substrate,making connections with sets of interconnect elements for contacting thesemiconductor devices while they are a part of the wafer. The interposeris useful for connecting two electronic components generally, and forperforming testing, exercising and burn-in in particular. The followingdescription and drawings are illustrative of the invention and are notto be construed as limiting the invention. Numerous specific details aredescribed to provide a thorough understanding of the present invention.However, in certain instances, well-known or conventional details arenot described in order to not unnecessarily obscure the presentinvention in detail.

Certain terms are utilized throughout this document and as such areintended to have the meanings provided below:

The terms “cantilever” and “cantilever beam” are used to indicate thatan elongate structure is mounted (fixed) in one region, with anotherregion free to move, typically in response to a force acting with acomponent transverse to the longitudinal axis of the elongate structure.

The term “resilient”, as applied to contact structures orinterconnection elements, indicates structures that exhibit primarilyelastic behavior in response to an applied load. The free-standing,resilient interconnection elements of the present invention are aspecial case of either compliant or resilient contact structures.

The term “electronic component” includes, but is not limited to:interconnect and interposer substrates; semiconductor wafers and diesmade for example of any suitable semiconducting material such as silicon(Si) or gallium-arsenide (GaAs); interconnect sockets; test sockets;sacrificial members, elements and substrates, semiconductor packages,including ceramic and plastic packages, chip carriers; passivecomponents such as resistors or capacitors, and connectors.

Turning to address the present invention in detail, FIGS. 3 a and 3 billustrate exemplary interconnect assemblies. The interconnect assembly1000 is shown to include an interposer 1002. Interposer 1002 includes asubstrate 1004 with a first surface and a second surface upon each ofwhich surfaces are disposed a plurality of resilient contact elements,1006 and 1008. In FIG. 3 a, an interposer 1002 establishes contactbetween a wafer 1012 and a wafer contactor 1010 through pressurecontacts applied to the contact elements 1006 and 1008. Wafer 1012 issecured to a base support 1016 and the housing assembly 1018 supportscontactor 1010. As shown in FIG. 3 a, substrate 1004 has disposedthereupon one or more compression stops 1014 for preventingover-compression of the resilient contact elements 1006 and 1008, aswill be explained more fully in the discussion herein below.

While a single compression stop 1014 will function to preventover-compression, it is preferred to have a plurality of compressionstops disposed on substrate 1004. The height of the compression stops ispredetermined in order to define a first position when the resilientcontact elements are in mechanical and electrical contact with anothercontact elements. In one embodiment of the present invention, there isno need for compression stops on the bottom surface of substrate 1004since the rigid supports 1020 limit excessive movement of wafer 1012. Itshould be understood that compression stops similar to 1014 can beprovided on the bottom of interposer 1002 to protect the resilientcontact elements 1006.

In operation, pressure contact is applied to wafer 1012 moving thelatter in the z-direction toward wafer contactor 1010, thereby meetingand then compressing resilient contact elements 1008. When contactelements 1008 are compressed, resilient contact elements 1006 are alsocompressed thereby establishing mechanical contact between the terminalsof wafer 1012 and the terminals of the wafer contactor 1010. It shouldbe noted that the terminals of wafer 1012 and wafer contactor 1010 arenot shown in FIG. 3 a. Compression stops 1014 prevent over-compressionand thereby prevent damage of resilient contact elements 1008.

In general, a conformal or flexible substrate may be used as substrate1004 for performing wafer-level contacting or other types of applicationdiscussed herein or known to those skilled in the art. The use of aconformal substrate permits for compensation of non-flatness in an overall assembly of the type shown in FIG. 3 a.

FIG. 3 b shows an alternative embodiment of an interconnect assembly1030 including an interposer 1032, a wafer 1050 supported on a base 1044and a wafer contactor 1036. Wafer contactor 1036 is supported in housingassembly 1034. Interposer 1032 comprises a substrate 1040 and aplurality of contact elements 1046 on the top of substrate 1040, andanother set of contact elements 1048 attached to the bottom of substrate1040.

Interposer 1032 is a fully floating interposer, which is positioned awayfrom all stops or supports once fully assembled. Resilient contactelements 1046 and 1048 provide opposing forces (from wafer contactor1036 and wafer 1050, respectively) in order to maintain this position.The excessive movement of interposer 1032 toward either wafer 1050 orwafer contactor 1036 is arrested by placement constraints 1042 and 1038,respectively. In this instance, the addition of stops similar to 1014 ofFIG. 3 a may be necessary to control the deformation of the substrate ata point away from the locating structures 1042 and 1038.

Substrate 1004 (of FIG. 3 a) or 1040 (of FIG. 3 b) may be made of manymaterials, including for example, an organic dielectric such as printedcircuit board (PCB) materials, silicon, insulator coated metal sheeting,metal matrix composites, glasses or ceramics. In certain applications,it would be desirable to form the substrate 1004 from silicon. This isparticularly helpful in an assembly, which will be in close contact withan operating semiconductor device. Such devices generally become warmduring use, or perhaps during testing, and it is very helpful to connectto materials which have a similar coefficient of thermal expansion sothe active device and the contactor remain in a similar geometricalrelationship. Matching a silicon device to another silicon devise isparticularly desirable.

FIG. 4 a shows an interposer 1052 wherein the resilient contact elements1054 on the top surface of the substrate 1056 are similar inconstruction but displaced laterally with respect to the resilientcontact elements 1058 on the bottom surface of the substrate 1056. Alsoshown in FIG. 4 a are conducting traces 1060 through which electricalcontact is established between the resilient contact elements on the topand bottom surfaces of the substrate. FIG. 4 b shows a differentembodiment of an interposer 1062. The resilient contact elements 1064 onthe top surface of the interposer are shown to be constructeddifferently and at a different lateral separation than the resilientcontact elements 1066 on the bottom surface of interposer 1062. In theinterposer of FIG. 4 b, the lower surface of interposer 1062 may contacta standard electronic device such as a contactor while the upper surfaceof interposer 1062 is customized to mate with a specific electronicdevice. Accordingly, different designs of the contact elements mountedon an interposer as described hereinabove fall within the scope andspirit of the present invention. Such designs enable different types ofelectronic components to be interconnected.

FIG. 4 c shows an alternative embodiment of an interposer 1068. Theresilient contact elements 1070 on the top surface of interposer 1068are shown to be connected in a not 1:1 relationship with those elements1072 on the bottom surface 1074 of the interposer. In FIG. 4 c theinterposer substrate may contain wiring layers for power and grounddistribution, allowing coupling of signals between multiple devices onthe wafer under test, etc. Additionally, passive or active components1076 may be attached to bottom surface 1074. Alternatively, techniquesknown in the art for placing passive components such as resistors,capacitors or inductors, within the wiring substrate 1068, e.g.“embedded passives” may be used.

FIG. 4 d shows a different embodiment of an interposer 1078. Resilientcontact elements 1080 on the top surface 1082 of interposer 1078, aswell as resilient contact elements 1084 on the bottom surface 1086 ofinterposer 1078 are shown to be respectively connected to passive oractive components 1088 and 1090, which are attached to (oralternatively, though not shown, may be embedded in) the interposersubstrate. Capacitive elements for decoupling and/or resistive elementsfor isolation or termination may be included with the interposersubstrate. Resilient contact elements 1092 and 1094 are also located onthe top surface 1082 and bottom surface 1086 of interposer 1078 toenable electrical connection of the substrate for contactingsemiconductor devices.

By way of further explanation, in one type of an interposer, theposition of the contact elements located on the top surface of theinterposer (e.g., as discussed in connection with FIG. 3 a, contactelements 1008) are essentially directly above the position of thecontact elements located on the bottom surface of the interposer (inFIG. 3 a, contact elements 1006). In alternative embodiments (e.g., inFIG. 4 b), the positions of the top and bottom contact elements of aninterposer may not be aligned vertically. For example, correspondingcontacts may be at identical x-y coordinates, with different z valuesrelative to the interposer. In alternative embodiments, contact elementsof an interposer are re-positioned so that there is correspondence butdifferent spacing between the location of the “top” and the location ofcorresponding “bottom” contact elements.

It should also be appreciated that the interposer may also function as aspace transformer, to translate one pitch (distance from one contactelement to another) to another pitch on respective faces of thesubstrate. In FIG. 5, a space transformer 1100 is shown wherein thedesired space-transforming is accomplished by the substrate 1102 of thespace transformer. Alternatively, or in addition to this repositioning,it is possible to shape or position the individual resilient contactstructures (not shown) attached thereto. (More detail is provided inFIG. 23 and discussions relating thereto of U.S. Pat. No. 5,917,707,entitled “ Contact Structure for Interconnections, Interposers,Semiconductor Assembly,” the disclosure of which is incorporated hereinby reference as though set forth in full).

Space transformer substrate 1102 has a top (as viewed) surface 1102 aand a bottom (as viewed) surface 1102 b and is preferably formed as amulti-layer component having alternating layers of insulating material(e.g., ceramic) and conductive material. In this example, one wiringlayer is shown as including two (of many) conductive traces 1104 a and1104 b.

A plurality (two of many shown) of terminals (contact pads) 1106 a and1106 b are disposed on top surface 1102 a of space transformer substrate1102 at a relatively fine pitch (relatively close to one another). Aplurality (two of many shown) of terminals (contact pads) 1108 a and1108 b are disposed on bottom surface 1102 b of space transformersubstrate 1102 at a relatively coarse pitch (relative to terminals 1106a and 1106 b); i.e., further apart from one another). For example,bottom terminals 1108 a and 1108 b may be disposed at about 50-100 milor 1.2-2.5 millimeter pitch (comparable to printed circuit board pitchconstraints), and top terminals 1106 a and 1106 b may be disposed atabout 1-10 mil or 0.025-0.250 millimeter pitch (comparable to thecenter-to-center spacing of semiconductor die bond pads), resulting in a50:1 pitch-transformation. Top terminals 1106 a and 1106 b are connectedto the corresponding bottom terminals 1108 a and 1108 b, respectively,by associated conductors 1110 a/1112 a and 1110 b/1112 b, respectively,connecting the terminals to the conductive traces 1104 a and 1104 b,respectively. This is all generally well known, in the context ofmulti-layer land grid array (LGA) support substrates, and the like. Fora more detailed discussion of space transformers, the reader is directedto U.S. Pat. No. 5,974,662, entitled “Method of Planarizing Tips ofProbe Elements of a Probe Card Assembly,” issued on Nov. 2, 1999, thedisclosure of which is herein incorporated by reference as though setforth in full. Alternatively, an interposer of the present invention mayinclude a different pad pattern on one surface (i.e. “top” surface) thanthe other surface (i.e. “bottom” surface) with or without a change inpitch.

In the case of the use of semiconductors, through-holes are made throughthe semiconductor device for connection of the corresponding contactelements. Commonly assigned U.S. patent application Ser. No. 09/205,502entitled “Socket For Mating With Electronic Component, ParticularlySemiconductor Device With Spring Packaging, For Fixturing, Testing,Burning-In or Operating Such A Component”, the disclosure of which isincorporated herein as though set forth in full, discusses making suchthrough-holes. In this application, particular attention is directed toFIGS. 4a-4f, which are presented herein as FIGS. 6 a to 6 f.

FIGS. 6 a to 6 f show side cross-sectional views illustratingfabricating hourglass-like through holes in a semiconductor substrate.FIG. 6 a illustrates a first step of the process of one embodiment ofthe present invention. A layer 1204 of nitride is applied to a frontsurface of a substrate 1202 which is a piece of 1,0,0 silicon. The layerof nitride is patterned to have openings 1206. These openings 1206 maybe square, having cross-dimensions (S1) of about 150-250 μm, such asabout 200 μm. In a similar manner, a layer 1208 of nitride is applied toa back surface of the substrate 1202 and is patterned to have openings1210. Openings 1210 in the nitride layer 1208 may be square, havingcross-dimensions (S2) of about 150-250 μm, such as about 200 μm.Selected ones and in general, each, of openings 1206 is located directlyopposite a corresponding one of openings 1210. A pair of alignedopenings 1206 and 1210 will determine the location of a through-holeterminal formed in silicon substrate 1202. Openings 1206 and 1210 areillustrated as having the same cross-dimension as one another (i.e.,S1=S2), but as will be discussed herein below, this is not necessary andmay not be preferred in some implementations.

In one preferred embodiment, openings equivalent to openings 1206 and1210 are rectangular rather than square. Opposing openings can haverectangles oriented in parallel, or opposing openings could beorthogonal. In general, a rectangular opening will create a troughstructure rather than a point when etched. The relative dimensions ofeach need not be the same.

FIG. 6 b illustrates a next step wherein the substrate 1202 is etchedwithin openings 1206 and 1210, nitride layers 1204 and 1208 acting asmasking material to prevent etching other than at openings 1206 and1210. A suitable etchant is potassium hydroxide (KOH). Other suitableetching agents include NaOH and strong bases. A feature of 1,0,0 siliconis that it will etch in a strong base solution at an angle, the anglebeing 53.7°. The etch proceeds according to the crystal lattice of thesilicon. Thus, it is preferred that openings 1206 and 1210 be orientedto align with the crystal lattice. The orientation of the lattice isknown and generally indicated by a notch in the generally circular waferof silicon.

Etching from only one side may give a pyramid shaped pit extending intothat side of the substrate if the etching process is stopped prior toreaching a pointed pyramidal feature. The dimensions of the pit arecontrolled by the dimension and orientation of the opening within whichthe etching occurs, and the etch angle of 1,0,0 silicon. The etchingcomes to a halt when there is no remaining exposed silicon on thesurface of the substrate. In general, starting with a square opening, apyramid-shaped pit is created. If the etch is not driven to completion,a truncated pyramid can be formed. Where the opening for etching isrectangular, a trough structure will be formed.

In a preferred embodiment, etching is from both sides, and twopyramid-shaped pits 1212 and 1214 (as shown in FIG. 5 b) “grow” towardone another. By ensuring that the openings are sufficiently wide, andthe substrate is sufficiently thin, pyramid-shaped pits 1212 and 1214will grow into one another (overlap), resulting in the“hourglass-shaped” through-holes illustrated in FIG. 6 b. If desired,the pits may be allowed to “over-etch” so that nitride layers 1204 and1208 slightly overhang the pit openings. Once etching is done, nitridelayers 1204 and 1208 may be removed, by preferential etching.

Etching this hourglass forms a “via” in the silicon substrate. Vias arewidely used in many electronic products such as semiconductor devicesand multilayer substrates. This new via will be made electricallyconducting, then can be used in many of the ways known for using vias.

FIG. 6 c illustrates a next step wherein substrate 1202 is re-nitrided,such as by thermally growing a very thin layer 1216 of nitride on allthe surfaces of substrate 1202, including within the sidewalls of pits1212 and 1214. This nitride functions in part to insulate the body ofthe semiconductor substrate from any subsequently applied conductivematerial. Alternatively, a layer of silicon oxide, or other organic orinorganic insulating coating may be applied to the substrate.

FIG. 6 d illustrates a next step wherein the entire substrate 1202 iscoated (e.g., sputter-coated) with a thin layer 1218 oftitanium-tungsten (TiW), then a thin seed layer 1210 of gold (Au).Representative dimensions and useful methods and materials are set forthin detail in co-pending, commonly assigned U.S. patent application Ser.No. 09/032,473, filed Feb. 26, 1998, entitled “Lithographically DefinedMicroelectronic Contact Structures,” the disclosure of which isincorporated herein by reference as though set forth in full.

FIG. 6 e illustrates a next step wherein layer 1230 of masking material,such as photoresist, is applied to both sides of substrate 1202 andpatterned to have openings aligned with pits 1212 and 1214. The seedlayer 1220 within the pits is not covered by the masking material. Then,one or more layers of a conductive material 1232, such as nickel, copperor gold, is deposited, such as by plating, onto exposed seed layer 1220within pits 1212 and 1214.

FIG. 6 f illustrates a next (final) step wherein masking layer 1230 isremoved (such as by rinsing off), and the unplated part of seed layers1218 and 1220 are removed (such as by selective chemical etching),leaving conductive material 1232 within and bridging pits 1212 and 1214,thereby forming a conductive via through substrate 1202. This provideselectrical continuity between pit 1212 and pit 1214. At the same time asthe vias are metallized, traces may be patterned on the opposing facesof the substrate to allow for more functionality or redistribution.Further details of an interposer substrate with through-hole typeterminal can be found in the aforementioned U.S. patent application Ser.No. 09/205,502.

FIG. 6 g illustrates an interim temporal step in the process justdescribed. When pits 1212 and 1214 (see FIG. 6 b) are first beingetched, they “grow” towards one another. In the case that openings 1206and 1210 (see FIG. 6 a) have the same cross-dimension (both are “S1”),the growing pits should be symmetrical with one another, one being themirror image of the other, as illustrated.

FIG. 6 h illustrates an interim temporal step (compare FIG. 6 g) in theprocess, in a case where openings 1206 and 1210 (see FIG. 6 a) do nothave the same cross-dimension, for example, opening 1206 has a largercross dimension than opening 1210 (i.e., S1/S2). Here, it can beobserved that pits 1244 and 1246 (compare 1212 and 1214) grow intosubstrate 1242 (compare 1202) at the same rate, but that pit 1246 hasreached its apex and terminated its growth. Pit 1244 will continuegrowing until etch self-terminates. The designer can select a thicknessof substrate 1202 and dimensions of openings 1206 and 1210 to permitthis etching pattern, or another selected etching pattern.

FIG. 6 i illustrates an interposer substrate 1252 (compare 1242) whereinthe process has started with openings (compare 1206 and 1210) that donot have the same cross-dimension, as in the case discussed with respectto FIG. 6 h. Here it can be observed that pit 1254 (compare 1244) iswider and deeper than pit 1256 (compare 1246). FIG. 6 i also illustratesthe conductive material 1258 deposited onto the seed layers (not shown)in pits 1254 and 1256.

For certain resilient contact elements, as used in the interposer (orspace transformer) embodiments of the present invention, a tip structurecan be fabricated as an end of each interconnect element. As shown inFIG. 7 a, tip structures 1320 (only two tip structures are shown in theview of FIG. 7 a, for illustrative clarity) are aligned with the tips ofthe interconnection elements (contact element) 1332, using standardflip-chip techniques (e.g., split prism), and the assembly is passedthrough a brazing furnace to reflow the joining material 1324, therebyjoining (e.g., brazing) the prefabricated tip structures 1320 to theends of the interconnection elements 1332.

With respect to the fabrication of composite interconnection elementshaving pre-fabricated tip structures, FIG. 7 a, shows the fabricationmethod at a certain step prior to tip attachment. As shown in FIG. 7 a,a silicon substrate or wafer 1302 is used as a sacrificial substrate. Alayer of titanium 1308 is deposited on the top surface of substrate1302, and a layer of aluminum 1306 is deposited atop titanium layer1308. A layer of copper 1310 is deposited atop aluminum layer 1306. Thealuminum layer serves as a release layer. Using a suitable etchant, thealuminum is preferentially (to the other materials of the assembly)etched away, and the silicon substrate 1302 simply “pops” off, resultingin an electronic component having interconnection elements, each havinga prefabricated tip structure, as illustrated in FIG. 7 b. Note that thejoining material 1324 has reflowed as “fillets” 1325 on end portions ofthe interconnection elements 1332. In a final step of the process, theresidual copper (1308) is etched away, leaving tip structure 1320 with adesired contact metallurgy exposed for making pressure connections toother electronic components. Alternatively, the brazing (soldering)paste 1324 is omitted, and instead, a layer of eutectic material (e.g.,gold-tin) is plated onto the resilient interconnection elements prior tomounting the contact tips (1320) thereto.

More detail regarding this tip attachment can be found in the U.S. Pat.No. 5,829,128, entitled “Method of Mounting Resilient Contact Structuresto Semiconductor Devices.” It is within the scope of this invention thatthis technique can be used to join (e.g., braze or solder)pre-fabricated tip structures to ends of non-resilient interconnectionelements, resilient interconnection elements, and compositeinterconnection elements, which are fabricated directly upon theterminals of the semiconductor device. Other structures of andtechniques for fabricating tip structures using sacrificial substratesare disclosed in U.S. Pat. No. 5,994,152, entitled “FabricatingInterconnects and Tips Using Sacrificial Substrate,” issued on Nov. 30,1999, to Khandros et al., the disclosure of which is herein incorporatedby reference as though set forth in full.

In FIGS. 8 a, 8 b and 8 c, contact tip structures that can be integratedinto the present interposer are shown. Further contact tip structuresand discussions and figures in association thereto are presented incommonly assigned U.S. patent application Ser. No. 08/819,464, entitled“Contact Tip Structures For Microelectronic Interconnection Elements AndMethods of Making Same,” filed on Mar. 17, 1997, the disclosure of whichis herein incorporated by reference as though set forth in full. In FIG.8 a, a contact tip structure 1420 is shown to have a flat contactsurface. These contact tips are shown as integrated onto a “cobra” typebuckling beam assembly adapted for use as interposer structure. For manypressure contact applications, a spherical or very small surface areacontact tip urging against a nominally flat-surfaced terminal of anelectronic component is preferred. In other applications, the surface ofthe contact tip structure will preferably have projections in the shapeof a pyramid, a truncated pyramid, a cone, a wedge, or the like.Techniques for fabrication of such contact tip structures are presentedin the aforementioned 08/819,464 application.

In FIG. 8 b, one of the plurality of elongate contact tip structures1435 is shown with each structure having a projecting pyramid-shapedcontact feature 1430 projecting from a surface thereof. It is thisprojecting contact feature that is intended to make the actual contactwith a terminal (not shown) of an electronic component (not shown).

As shown in FIG. 8 b, the pyramid-shaped contact feature 1430 may besuitably polished (abraded) off, which will configure the pyramid-shapedfeature as a truncated pyramid-shaped feature. The relatively small flatend shape (e.g., a square measuring a few tenths of a mil on a side, onthe order of 1-10 microns), rather than a truly pointed end shape, willin many applications be sufficiently “sharp” to make reliable pressureconnections with terminals (not shown) of electronic components (notshown), and may tend to wear better than a truly pointed feature formaking repeated (e.g., thousands of) pressure connections to electroniccomponents, such as might be expected in an application of the tippedinterconnection elements of the present invention for a wafer-levelcontactor. The desired tip shape and feature definition will depend onthe nature of both the contact tip and the mating surface material andmorphology. Design of these mating contact elements for optimumperformance would have to be undertaken as part of the overall designexercise associated with building the interposer assembly itself.

As shown in FIG. 8 c, in subsequent processing steps wherein a contacttip structure is fabricated (such as described in the aforementioned08/819,464 patent application), one or more (four shown) “dimple”contact features 1418 project from the main body of the resultingcontact tip structure 1425.

There are several variations of the “dimple” contact features 1418. Forexample, resilient contact structures can be fabricated on the base 1425with tips of various shapes and distances from their bases.Alternatively, it is possible to reposition the contact structures onthe base 1425 by providing conductive traces so that the base is movedaway from a primary position to a desired location.

One useful embodiment of an interposer embodiment of the presentinvention having two different contact pad patterns, as describedhereinabove, is for mating with two different designs of components,i.e. components with different types of terminals. That is, in oneembodiment of the present invention, one surface of the interposer (suchas the “top” surface) includes a truncated pyramid contact pads and anopposite surface of the interposer (the “bottom surface) includescone-shaped contact pads. Any of the various types of contact pads, asrecited in the 08/819,464 application or known to those of skill in theart, may be integrated into the various embodiments, discussed herein,of the present invention interposer.

Commonly assigned U.S. Pat. No. 5,829,128 (the “128 patent”), entitled“Method of Mounting Resilient Contact Structures To SemiconductorDevices” and issued to Eldridge et al. on Nov. 3, 1998, disclosessubstrates with conductive material. The disclosure of this patentdocument is herein incorporated by reference as though set forth infull. The '128 patent teaches exemplary substrates upon which resilientinterconnect elements are fabricated. In particular, in FIGS. 8 a-8 e,there is disclosed a silicon wafer used as the sacrificial substrateupon which tip structures are fabricated, and that tip structures sofabricated may be joined (e.g., soldered, brazed) to resilient contactstructures that already have been mounted to an electronic component.

There is further disclosed in the '128 patent resilient contactstructures, as shown in FIG. 7 a, wherein a “dead space” is used toposition an electrical component such as a decoupling capacitor. Thisconcept of piggybacking passive (such as capacitors and resistors)and/or active components between a substrate and a wafer and between asubstrate and a wafer contactor is integrated into an embodiment of thepresent invention, as shown in and discussed in connection with FIGS. 9a and 9 b herein.

In FIG. 9 a, an interposer 1500 is shown connected to a plurality (twoof many shown) of semiconductor devices (dies) 1502 and 1504 prior tosingulating (separating) the devices from a semiconductor wafer (wafernot shown in FIG. 9 a). A boundary between the two devices is indicatedby the notch 1506. (The notch may or may not actually exist, andrepresents the position of a kerf (line) where the wafer will be sawedto singulate the devices.)

In FIG. 9 a, the interposer 1500 is further shown to include aninterposer substrate 1510 having a plurality of resilient contactelements 1508 disposed on a top surface of the substrate 1510 and aplurality of resilient contact elements 1536 disposed on a bottomsurface of the substrate 1510. The contact elements 1508 and 1536 arefabricated on the substrate 1510 in manners as described and/orincorporated by reference hereinabove. The wafer on which the devices1502 and 1504 are disposed includes terminals 1512 for being broughtinto mechanical and electrical contact with the contact elements 1508. Awafer contactor 1532 has disposed thereon a plurality of contact pads1534 for being brought into mechanical and electrical contact with thecontact elements 1536. The wafer on which the devices 1504 and 1502 aredisposed is brought to bear against the substrate 1510, or vice-versa,so that each of the contact pads 1512 effects a pressure connection witha corresponding one of the resilient contact elements 1508. Similarly,the wafer contactor 1532 is brought to bear against the substrate 1510,or vice-versa, so that each of the contact pads 1534 effects a pressureconnection with a corresponding one of the resilient contact elements1536. In this manner, a technique is provided for performing burn-in ofunsingulated semiconductor devices in wafer form

The substrate 1510 can be of any of the materials discussed hereinabove,such as a printed circuit board (PCB), ceramic or silicon.

The wafer (devices 1502, 1504 and additional devices) is aligned withthe substrate 1510, using any suitable alignment means (such as locatingpins, not shown) so that each resilient contact element 1508 bears upona corresponding pad 1512. Similarly, the wafer contactor 1532 is alignedwith the substrate 1510 using any suitable alignment means so that eachresilient contact element 1536 bears upon a corresponding pad 1534.

An important advantage accruing to the interposer 1500 illustrated inFIG. 9 a is that the resilient contact elements 1508 and 1536 stand ontheir own (disassociated from one another), and can be fabricated toextend to a significant distance from the substrate 1510. This isimportant, in that it provides an appreciable “dead space” both betweenthe resilient contact elements 1508 (and similarly between the resilientcontact elements 1536) and between the opposing surfaces of the die(e.g., 1502) and the substrate 1510 (and similarly between the opposingsurfaces of the wafer contactor 1532 and the substrate 1510). “Deadspace” 1514 and “dead space” 1530 are disposed, as shown in dashedlines, on either surface of the substrate 1510. In many semiconductorapplications, it is beneficial to provide decoupling capacitors as closeto interconnections as possible. According to the present invention,there is ample space for decoupling capacitors to be located in theotherwise “dead spaces” 1514 and 1530. As depicted in FIG. 9 a, suchdecoupling capacitors can be mounted to the wafer on which the die 1502and 1504 are disposed and/or to wafer contactor 1532. As is shown inFIG. 9 b, the decoupling capacitors or other components may be connectedto substrate 1510 of interposer 1500. It should be appreciated thatpassive elements, other than capacitors, or in addition thereto, such asresistors, may be disposed in the “dead spaces” 1514 and 1530. Further,active elements may be disposed in the “dead spaces” 1514 and 1530.

For additional details of various types of contact elements (resilientand otherwise) for effecting pressure connections between electroniccomponents, such as done in connection with the present invention, thereader is directed to commonly assigned U.S. patent application Ser. No.08/819,464 entitled “Contact Tip Structures for MicroelectronicInterconnection Elements,” filed on Mar. 17, 1997, the disclosure ofwhich is herein incorporated by reference as though set forth in full.Any of the various contact elements disclosed in the referenced documentcan be used as interconnection elements, e.g., interconnection elements1006 and 1008 of FIG. 3.

In one embodiment of the interposer of the present invention,microelectronic contact structures are fabricated lithographically.Examples of such contact structures and fabrication thereof aredisclosed in detail in co-pending, commonly assigned U.S. patentapplication Ser. No. 09/032,473, referenced and incorporatedhereinabove. In particular, FIGS. 2L and 2M of the referencedapplication, which are presented herein as FIGS. 10 a and 10 b,respectively, illustrate an assembly 1600 in which a free-standingcontact structure 1660 is attached at its base end 1662 to an electroniccomponent 1602, the main body portion 1666 of structure 1660 ispositioned away from the surface of the electronic component 1602, andits tip end portion 1664 having a topography extending even farther fromthe level of the main body portion 1666. The sloped region 1663 of thebase end 1662 of the resulting contact structure 1660 is clearly visiblein these figures.

In FIGS. 10 a and 10 b, contact element 1666 is mounted on an electronicdevice comprising a silicon substrate 1602, a passivation layer 1604disposed on the surface of the silicon substrate 1602 and an opening1606 extending through the passivation layer 1604 to the metallic pad1608. Commonly, there is a plurality of such contact pads on anelectronic device.

Directly on top of substrate 1602, there is a passivation layer 1604covering the surface of substrate 1602 except for contact pad 1608.Contact pad 1608 is disposed over the surface of substrate 1602.

Next, a layer of conductive material 1610 is deposited on top of thepassivation layer. Conductive layer 1610 is in contact with contact pad1608. Passivation layer 1604 assists in bonding conductive layer 1610 topassivation layer 1604.

Directly on top of conductive layer 1610, there is a seed layer 1650,with a curved portion 1623. The seed layer 1650, when patterned, servesas a precursor for a contact structure to be fabricated on theelectronic device. The contact structure is in the form of an elongatemass of conductive material comprising a base end 1662, a main bodyportion 1666 and the tip end 1664. The main body portion 1666 of thecontact structure is in a plane, which is approximately parallel to thesurface of the substrate 1602. Contact structure 1660 is free-standingsecured by its base 1662 to substrate 1602, with its tip end free tomake contact with a terminal of another electronic device. Contactstructure 1660 reacts to applied forces by resiliently and/orcompliantly deflecting in any or all of the x, y and z axis. Furtherdetails of various types of contact elements and fabrication thereof areshown in the aforementioned U.S. patent application Ser. No. 09/032,473.

FIG. 11 shows another embodiment of the interposer in accordance withthe present invention. Interposer 1720 includes a plurality of solderballs 1704 disposed on the top surface of interposer substrate 1710 forestablishing contact between interposer 1720 and the terminals orcontact pads (not shown) of an electronic component 1700. Interposer1720 also includes a plurality of resilient contact elements 1706,disposed on the bottom surface of substrate 1710 for establishingcontact between interposer 1720 and the terminals or contact pads (notshown) of an electronic component 1702. In this manner, interposer 1720permits mechanical and electrical contact between electronic components1700 and 1702. Interposer substrate 1710 has disposed thereupon aplurality of compression stop structures 1708 for limiting compressionof contact elements 1706 upon pressure contact applied between component1700 and substrate 1710.

FIG. 12 shows yet another embodiment of the present invention wherein aninterposer 1750 has disposed on one surface thereof (in FIG. 12, thissurface is shown as the top surface of a substrate 1754) a plurality ofspring contact elements 1752 that are fabricated using lithographictechniques. Methods for fabricating such contact elements are disclosedin commonly assigned U.S. patent application Ser. No. 08/802,054, andits corresponding PCT application WO 97/43656, the disclosure of whichis herein incorporated by reference as though set forth in full. In thisreference document, FIGS. 6a-6c particularly illustrate a technique forfabricating contact elements 1752.

In FIG. 12, contact elements 1752 bend to a compressed state in adirection as shown by directional arrow 1758 when the electroniccomponent 1762 is pressed towards the substrate 1754. Additionally,contact elements 1756 bend to a compressed state in a direction shown bydirectional arrow 1759 when the electronic component 1764 is pressedtowards the substrate 1754. The contact elements 1756 are shown to havea smaller pitch than the contact elements 1752. Components 1762 and 1764include contact pads 1770 and 1768, respectively, for connecting to thecontact elements 1752 and 1756.

FIG. 13 depicts an interposer in accordance with an embodiment of thepresent invention. Interposer 1800 comprises an interposer substrate1802, resilient contact elements 1816 and 1818, which are mounted onboth sides of the substrate 1802, as well as two sets of tile substrates1804, 1806 and 1808, and 1810, 1812 and 1814. One set of the tilesubstrates, tile substrates 1804, 1806 and 1808, are located atop ofinterposer substrate 1802, and the other set of the tile substrates,tile substrates 1810, 1812 and 1814, are located at the bottom ofinterposer substrate 1802.

The resilient contact elements (a plurality of resilient contactelements 1816, disposed on a top surface of the substrate 1802, throughcontact pressure with the top tiles, and a plurality of resilientcontact elements 1818, disposed on a bottom surface of the substrate1802, through pressure contact with the bottom tiles) connect the pairof tile substrates 1804 and 1810, and similarly connect the pairs 1806and 1812, and 1808 and 1814. Tile substrates 1804, 1806 and 1808 may bepart of an electronic component substrate such as a wafer (not shown inFIG. 13), including semiconductor devices or passive components.Similarly, tile substrates 1810, 1812 and 1814 may be an integral partof another electronic component, such as a wafer contactor, probetester, or the like. As the two layers of the tile substrates (1804 and1810, 1806 and 1812, and 1808 and 1814) are pushed towards each otherthe resilient contact elements 1816 and 1818 are compressed therebyexerting pressure and establishing electrical connection between thetiles substrates.

By way of further explanation, tile substrates, 1804, 1806 and 1808, maybe disposed on a wafer and tile substrates 1810, 1812 and 1814 may be ona tester. Interposer 1800 permits the entire semiconductor wafer to betested, probed or burned-in (generally referred to as “exercised”) atthe same time. Multiple die sites, corresponding to the substrate tile1804, 1806 and 1808, on a semiconductor wafer are readily probed byemploying the substrate tiles 1810, 1812 and 1814 via the interposersubstrate 1802. In addition, substrate tiles on a tester, such as 1810,1812 an 1814 may be arranged in order to optimize probing of an entirewafer.

FIG. 14 shows yet another embodiment of an interposer in accordance withthe present invention wherein two types of contact elements are employedon top and bottom surfaces of an interposer 1830 for making contact totwo electronic components. In FIG. 14, at the top surface of theinterposer substrate 1870, a plurality of contact elements 1861 and 1862are affixed, for example, in the manner described with respect to FIG.13c or FIG. 22b of commonly assigned PCT Application No. PCT/US99/28597,entitled “Lithographic Contact Elements” filed on Dec. 1, 1999, whichclaims priority to U.S. patent application Ser. No. 09/205,023 and“Lithographic Contact Elements,” filed on Dec. 2, 1998, patentapplication Ser. No. 09/205,022 (the disclosures of which are hereinincorporated by reference as though set forth in full), so that tipportion ends 1872 and 1874 make pressure connections with terminals 1866of electronic component 1864, such as a semiconductor device, or an areaof a semiconductor wafer (not shown) containing a plurality ofsemiconductor devices. Similarly, at the bottom of substrate 1870, aplurality of contact elements are affixed, two of which are shown to be1840 and 1842. Tip structures 1854 and 1856 of the contact elements 1840and 1842 make pressure connections with terminals 1858 of the electroniccomponent 1850. Electronic component 1850 may be a wafer containing aplurality of semiconductor devices, a contactor, a test device or otherelectronic component described hereinabove. Thus, mechanical andelectrical contact is established between the electronic components 1850and 1864.

It should be apparent from the foregoing discussion that interposers maybe designed to interconnect a wide variety of electronic components. Bysuitable choice of contact elements on both surfaces of the interposer,as can be appreciated, electronic components having different pitch,different lengths or different contact pads having diverse features maybe interconnected using the apparatus and methods of the presentinvention.

As shown in FIG. 15, interposer 1900 can be implemented in conjunctionwith a pressure activated contactor. As depicted in FIG. 15, interposer1900 has contact elements 1902 and 1904 disposed on each side, and thedevice under test is a complete semiconductor wafer 1906. Wafer 1906 isplaced against a chuck 1908. A wiring substrate or layer 1910 ispositioned above interposer 1900. Wafer 1906 includes a plurality ofcontact pads 1912 and wiring substrate 1910 includes a plurality ofterminals 1914. Pressure, as indicated by directional arrow 1916 isutilized for enabling proper contact between interposer 1900 and wafer1906, more specifically between contact elements 1904 and contact pads1912, and between interposer 1900 and wiring substrate 1906, morespecifically, between contact elements 1902 and terminals 1914. Anexemplary pressure contact arrangement is discussed in commonly assignedU.S. patent application Ser. No. 09/376,759 entitled “ElectricalContactor, Especially Wafer Level Contactor, Using Fluid Pressure,”filed on Aug. 17, 1999, the disclosure of which is herein incorporatedby reference as though set forth in full. In this regard, it should beappreciated that various arrangements of stop structures, for example asdiscussed above in connection with FIGS. 3 a and 3 b, may be implementedin the arrangement of FIG. 15.

FIG. 16 illustrates an instantiation of the system 1900 of the presentinvention, illustrating a number of features, which would be applicableto a variety of instantiations of the technique of the presentintention. These features are a plurality of ASICs 2006, mounted to aninterconnection (support) substrate 2008, and a plurality of DUTs 2002connected to the ASICs 2006, through an interposer 2001, havingdouble-sided resilient contact elements as discussed hereinabove andindicated by the arrows 2003. A power supply 2018 provides power, viathe interconnection substrate 2008, via ASICs 2006 and via interposer2001, to the DUTs 2002 to power them up for operation. This isespecially useful for testing and also useful for burn-in.

Host controller 2016 provides signals to the ASICs 2006 via theinterconnection substrate 2008. Relatively few signals, for example aserial stream of data, need to be provided to each ASIC in order toindividually control the plurality (one of many shown) of ASICs 2006mounted to the interconnection substrate 2008. ASICs 2006 contact theresilient elements on the top surface of the interposer 2001 via thecontact pads 2020. In one embodiment of the present invention, ASICs2006 may be mounted adjacent to the contact pads 2020 thereby minimizingthe signal path between ASICs 2006 and DUTs 2002. However, it may not bealways possible to locate all the ASICs close to the contact pads 2020so that in an alternative embodiment of the present invention, the ASIC,being farther from the contact pads 2020, are wired to the contact pads2020.

The instantiation illustrated in FIG. 16 is an example of a system fortesting DUTs, for example, memory devices. Host controller 2016 isconnected to the plurality of ASICs 2008 through a data bus which needsvery few (e.g., four) lines: a line for data out (labeled DATA OUT), aline for data back (labeled DATA BACK), a line for resetting the ASICs(labeled MASTER RESET), and a line conveying a clock signal (labeledCLOCK). All of the ASICs mounted to the interconnection substrate areconnected to these FOUR “common” lines that are connected in theinterconnection substrate to all of the ASICs. This illustrates thesimplicity in realizing (i.e., manufacturing) an interconnectionsubstrate (2008), which is adapted in use to test a plurality ofcomplicated electronic components (DUTs).

Power (labeled +V) and ground (labeled GROUND) connections are similarlyeasily dealt with in the interconnection substrate. Essentially, onlytwo lines are required in the interconnection substrate, which arepreferably realized as planes (i.e., a power plane and a ground plane)in a multiplayer interconnection substrate. More details may be found incommonly assigned PCT Publication No. WO/97,43656, entitled “Wafer LevelBurn-in and Test”, the disclosure of which is herein incorporated byreference as though set forth in full.

Communication, power and testing may be handled by a suitable ASIC andcontrol and support system, such as discussed in U.S. Pat. No.5,497,079, issued to Yamada et al. and owned by Mitsubishi, Inc. and PCTPublication No. WO/97,43656.

A problem associated with prior art techniques of powering up aplurality of DUTs is voltage drop through the interconnection substrate.This problem is overcome by the present invention by providing increasedvoltage to the ASICs (2006) and incorporating a voltage regulator(labeled VOLTAGE REGULATOR) in the ASICs.

One having ordinary skill in the art to which the present invention mostnearly pertains will recognize that additional functionality, notspecifically illustrated, may readily be incorporated into the ASICs.For example, providing each ASIC with a unique address and an addressdecoding function, to individualize its response to a serial stream ofdata coming form the controller 2016.

The operation and further details of a prior art system that shares someof the same structures as disclosed in FIG. 16 is discussed in PCTPublication No. WO 97/43656. In FIG. 16, each ASIC can readilycommunicate over a large number of interconnection elements (springcontact elements) with the DUT to which it is connected through theinterposer 2001. Additionally, the ASICs resident on the interconnectionsubstrate can communicate multiples of the large number of connectionsbetween the ASICs and the DUTs.

In the event of use of ASICs on the tester side of the substrate, a 1:1correspondence is typically required between the tester pads and the DUTpads, unless a multiplexing circuitry is built into the DUT wafer. Thesystem as described accomplishes this by using the ASICs connecteddirectly to the WUT via the interposer, and then a small number ofconnections from the ASICs to the tester board.

In the interposer of the present invention, if active components orother busing schemes are built into the interposer, the overall“connection count” can substantially be decreased, most notably in theinterconnection substrate. For example, an 8-inch wafer may contain 50016 Mb DRAMs, each having 60 bond pads, for a total of 30,000connections. Using the technique of the present invention, these 30,000connections are directly made between the ASICs and the DUTs; and, fromthe ASICs, through the interconnection (support substrate), back to thehost controller, e.g., power (2 lines) and a serial signal path (as fewas two lines, including the ground line from the power source). This isin marked contrast to techniques of any prior art which, even if it wereto use the ASICs of the present invention or similar instrumentality,would require connecting the ASICs via an interconnection substrate tomeans interconnecting the interconnection substrate to the DUTs. Thepresent invention completely eliminates this problem, and substantiallyreduces the numbers of nodes required on the interconnection substrate,by effecting connections directly between the ASICs and the DUTs.

Another aspect of the present invention is in the use of the variousinterposers presented and discussed herein as an in-circuit emulator(ICE) for use in testing the functionality of a product, such as anintegrated circuit, that is yet unavailable. In such a case, as known tothose skilled in the art, an ICE is use to create the same functions asthose that would eventually be carried out by the product in developmenttherefore expediting the testing process of the product.

FIG. 17 shows an interconnect assembly 2100 including a host controller2116, a power supply 2118 and a contactor system 2130 in accordance withanother embodiment of the present invention. The contactor system 2130comprises base plates 2104 and 2104 a, an interconnection substrate2108, a plurality of ASICs 2106 a-2106 d, a plurality of DUTS 2102a-2102 d and an interposer 2140. Interposer 2140 may be any of theembodiments disclosed hereinabove. Interposer 2140 comprises a substrate2141 and resilient contact elements 2142.

The host controller 2116 is coupled to the interconnection substrate2108 through the interface line 2148 and the power supply is coupled tothe interconnection substrate 2108 through the transmission line 2150.Guide pins 2112 allow the upper base plate 2104 a to be lowered so thatthe ASICs 2106 a-2106 d come in contact with the resilient contactelements 2142 on the upper side of the substrate 2140. Resilient contactelements 2142 on the lower side of the substrate 2140 rest against theDUTs 2102 a-2102 d. At this point electrical contact is establishedbetween the various ASICs and DUTs making it possible to test and probevarious DUTs at the same time on the wafer-level.

Base plate 2104 a is stopped from moving too far and over compressingthe resilient contact elements 2142 by the compression stops 2144.Additionally, compression stops may be disposed between 2140 and/or 2106and/or 2102 as discussed above in connection with FIG. 3 b.

Power supply 2118 provides the power required for testing the DUTs andthe host controller 2116 manages the various aspects of testingperformed on the DUTs, as discussed herein below.

In FIG. 18 a, an interposer 2200 is shown comprising a substrate 2202and various beam-type resilient contact elements such as 2204. The mainfeature of interposer 2200 is that the resilient contact elements arenot aligned so that different pitch lengths may be accommodated on thetwo surfaces of the interposer. Shown in FIG. 18 a is a smaller pitchlength 2206 on the bottom surface of the interposer and a longer pitchlength 2208 on the top surface of the interposer. In this way,interposer 2200 offers the flexibility of interconnecting differenttypes of devices. For example, one surface may be connected to a devicehaving a standard pitch pattern while the other surface may accommodatea device with a specific pitch.

In FIG. 18 b, there is shown, an interposer assembly 2210 with variouscontact elements mounted on a substrate 2212. Substrate 2212 includesthree through-holes. Each through-hole represents a possible variationon the way contact elements may be mounted on the substrate 2212. On thefirst through-hole 2214 is mounted two contact elements 2218 and 2216whose tips are offset as indicated by the arrow 2220.

At the second through-hole 2242 contact elements 2226 and 2228 aremounted on the bases 2224 and 2232. The compression stops 2222 and 2224are mounted directly on top of the bases 2232 and 2230, respectively. Inan alternative embodiment, the contact elements 2238 and 2240 aremounted on the through-hole 2244. However, the compression stops 2234and 2236 are mounted away from the contact elements 2238 and 2240, asshown in FIG. 18 b. Hence, various ways of attaching contact elements toan interposer are possible which fall within the scope and spirit of thepresent invention.

In the foregoing specification, the present invention has been describedwith reference to specific exemplary embodiments thereof. It will,however, be evident that various modifications and changes may be madethereto without departing from the broader scope and spirit of theinvention as set forth in the appended claims. The specification anddrawings are, accordingly, to be regarded in an illustrative rather thanin a restrictive sense.

1. An interposer comprising: a substrate having first and second opposedsides with a first set of terminals on the first side, a second set ofterminals on the second side, and a means of electricallyinterconnecting the terminals of the first and second sides; a first setof resilient contact structures, each having a portion connected to arespective one of the terminals of the first set of terminals, a firstcontact region distant from the substrate, and an elongate sectionextending from the portion to the first contact region, the elongatesection resiliently bending upon depression of the first contact regiontowards the substrate; and a second set of resilient contact structures,each having a portion attached to a respective one of the terminals ofthe second set of terminals, a contact region distant from thesubstrate, and an elongate section extending from the portion to thecontact region, the elongate section resiliently bending upon depressionof the contact region towards the substrate, wherein upon depression ofthe first and second contact regions, the interposer causes electricalcoupling of two devices. 2-35. (canceled)